The present invention relates in general to semiconductor technology, and more particularly to methods and structures for forming inter-electrode dielectric and gate dielectric in shielded gate trench FETs.
Shielded gate trench FETs are advantageous over conventional FETs in that the shield electrode reduces the gate-drain capacitance (Cgd) and improves the breakdown voltage of the transistor without sacrificing the transistor on-resistance. FIG. 1 is a simplified cross sectional view of a conventional shielded gate trench MOSFET. An n-type epitaxial layer 102 extends over n+ substrate 100. N+ source regions 108 and p+ heavy body regions 106 are formed in a p-type body region 104 which is in turn formed in epitaxial layer 102. Trench 110 extends through body region 104 and terminates in the drift region which is the portion of epitaxial layer 102 extending between body region 104 and substrate 100. Trench 110 includes a shield electrode 114 below a gate electrode 122. Gate electrode 122 is insulated from its adjacent silicon regions by gate dielectric 120, and shield electrode 114 is insulated from its adjacent silicon regions by a shield dielectric 112 which is thicker than gate dielectric 120.
The gate and shield electrodes are insulated from each other by a dielectric layer 116 also referred to as inter-electrode dielectric or IED. IED layer 116 must be of sufficient quality and thickness to support the potential difference that may exist between shield electrode 114 and gate electrode 122 during operation. In addition, it is desirable to have relatively low interface trap charges and dielectric trap charges in IED layer 116 or at the interface between shield electrode 114 and IED layer 116.
Conventional methods for forming the IED layer include thermal oxidation or chemical vapor deposition (CVD). Each of these methods has limitations. For example, the CVD process tends to produce lower quality dielectric and higher charges and traps. On the other hand, in thermal oxidation, both the device channel surface and the shield electrode are oxidized at the same time, and the thickness of the IED is limited by the target thickness of the channel gate dielectric. As a result, even though thermal oxidation often produces higher quality oxide, it is difficult to obtain the desired IED thickness.
Thus, there is a need for structure and method for forming shielded gate trench FETs that enable forming a high-quality IED to the desired thickness without being limited by the target gate dielectric thickness.